Blog entry

Why Nanoelectronics is better than Microelectronics?

By  Mehrdad Shaygan,  AMO.

Silicon integrated circuit technology, including transistors and other electronic components,  are dependent on micro- and nanoeletronic technologies. Regarding to the cost of transistor fabrication and high-volume production, integrated circuits are highly demanded in various applications in human activities such as telecommunication, medical, education and etc. To better understand the scale of the transistor manufacturing, the annual number of rice grain harvested on the earth is smaller than that of fabricated transistors. Figure 1 shows the number of transistors for a variety of microprocessors chips versus time introducing new enabling technologies.


Figure 1: The number of transistors per microprocessors chip over the years


In 1965, Gordon Moore as a co-founder of Intel Company reported that between 1958 and 1965, the number of component for integrated circuits had doubled every year. As can be seen in Fig. 2, exhibiting the number of transistors in some Intel processors, the number of transistors on chip has been doubled every about 24 months.


Figure 2: Number of transistors on Intel processors as a function of time

It is worth mentioning that by increasing the number of fabricated transistors, the cost of manufacturing decreases significantly. There are several reasons for shrinking the size of electronic devices such as lower energy consumption, more powerful information device and more predicted capacity for data storage. Thanks to fast progress of lithography techniques, making the components smaller and smaller on silicon wafer is achievable for processing data information. Although, the scaling down of the lithographically patterned transistors will face a limit in future but nanoelectronic might able to continue this process.

Among different types of electronic devices, transistors attract much attention due to their fascinating properties and applications. After the invention of the first transistor in 1947 by J. Bardeen and W. H. Brattain which was a point-contact transistor, a variety of transistors has been introduced to the market. Field effect transistor (FET) as a member of unipolar family with a faster and better performance at high frequency, has been widely used in different applications such as amplifiers, switch electronic signals and etc, in analog and digital circuits.

In order to extremely scale down the transistor keeping their reasonable performance characteristics, it is strongly needed to consider the generic structure and physical layout of the transistors. A FET, as common type of transistors used for amplifying the weak signals, consists of three terminals as source, drain and channel. In FETs, the height and width of the energy barrier determine the main operational characteristics of the transistors including device size, switching speed, operating voltage and OFF leakage current and etc. In MOSFET configuration as the modern microelectronic transistors, MOS abbreviation describes three main sectors of the FET namely metal as gate, oxide as separation layer and semiconductor as source. In this configuration, a gate electrode is separated by a thin layer of gate insulator such as SiO2, HfO2 and etc. The determining electric field is created between the gate electrode and the barrier height by applying a voltage. The width of this barrier is defined by device fabrication shown by some geometrical characteristics such as gate length (Lg) or channel length (Lch) and the critical feature size (F) with and assumption of Lg LchF . As can be seen in schematic view of a MOSFET (Fig.3a), gate controls over the scaling in optimized FET structure. The relation between gate oxide (Tox) and channel length (Lch) should follow Tox/lch ~ 1/30. In panels b and c, two representations of a binary switch are shown suggesting the generic topology for the ultimate scaled device. As one of the main fundamental issues for limiting the scaling down the MOSFET, critical feature size (F) plays a key role since quantum mechanical tunneling increases the OFF leakage current significantly (Fig. 3d). It is reported that the ultimate limit of FET defines as Lch=4-7 nm while the OFF-state leakage current becomes overwhelming.

Figure 3: (a) Schematic view of a FET; side and plan view of the device, (b) and (c), respectively; (d) limit of scaling down for FETs


Nevertheless, there is a limit of 50 nm for scaling down for MOSFET fabrications where the performance degradation starts due to loss of charge in the inversion layer and degradation of carrier mobility due to an increased scattering.

CMOS (Complementary Metal-Oxide-Semiconductor) as mostly used technology in microprocessor, memories, digital logic circuits, image sensors and etc, systematically utilizes n-type and p-type MOSFETs for ensured logical functions.  In this technology, the power consumption is low in OFF-state and it needs power just for switching. Moreover, it has less sensitivity to electronic noise compered to other technologies. It worth mentioning that shrinking the size of MOSFETs not only increases the performance speed but also decreases the energy consumption of the device due to decreased capacitance and increased current. Therefore, there is a continuous transition of lithography techniques to overcome the limit of 100 nm scale where it is the boarder of microelectronic to nanoelectronic. Due to well-developed techniques in deposition, pattering and characterization, the size of electronic components has been decreasing during the last decade from above 100 nm to about 20 nm today. Although, there is still an ongoing trend for smaller thickness of layers in MOSFETs such going below 10 atoms for oxide layer acting as gate separation layer but some technical issues need to be solved such as roughness. Moreover, as Table 1 depicts the performance projection for extremely scaled high-performance FETs provided by International Technology Roadmap for Semiconductor (ITRS) exhibiting an ultimate limit for scaling the MOSFETs as it discussed before.


Table 1: The performance projection for extremely scaled high-performance FETs provided by (ITRS)


As determining parameter in microelectronic, the accuracy of patterning should be carefully considered where technology nodes is defined. In a 90nm technology node, the definition is referred to the size of the transistors in a chip. There is a significant improvement in node technology in last decades as the 10 μm technology node reached to 22 nm in 2011. Moreover  the next generation will be at 16 and 11 nm as it shown in Fig.4.  


Figure 4: Evolution of technology nodes in semiconductor manufacturing processes in log scale.

Although there is enough motivation for shrinking the size of the transistors,   some issues should be addressed before reaching the limit. New phenomenon and physical changes such as quantum effects occur by entering to the nanoscale. Moreover, energy dissipation plays a key role since by shrinking the size of the electronic components, their density increases leading to higher heat dissipation through the whole system. Another limiting factor is the economical issues since the cost of fabrication for integrated circuits increases strongly by reducing the size of the components.
It is generally agreed by many researchers that the advent of nanoelectronic would solve the ongoing matters in scaling down the transistor technology. Since in nanoelectronic techniques smaller integrated circuits would be reachable in which they are not feasible to fabricate via conventional IC technology. The electronic devices are the fundamental elements of circuit design and technology, wherein silicon based transistors and copper wires are basic sectors in Very Large Scale Integration (VLSI) systems. It is believed that these systems would be replaced by nanoscale devices fabricated based on well-known nanoelectronic technologies such as carbon nanotubes, semiconductor nanowires and graphene. Literature is replete of their fascinating properties explain their novel applications. At the laboratory level, different types of devices based on these materials have been made such as resistors, diodes, switches, single electron transistors and electromechanical devices. Importantly, the main issue for such devices is ability to move and position the nanostructure on the device with a controllable way of alignment on the circuit.


A nanotransistor is a device in which the charge carrier transport is ballistic. The mean free path of the electrons, which is about 100 nm, is larger than the channel length of the nanotransistor. If the channel becomes shorter than 10 nm, charge carriers can tunnel from the source to the drain which increases charge leakage in the Off-state of the transistor. This drawback can be reduced using Silicon On Insulator (SOI) material and making fully depleted SOI devices. Multigate electrodes are used to reduce this gate leakage.